1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a data reading circuit for a semiconductor memory device.
2. Background of the Related Art
As shown in FIG. 1, a data reading circuit for a semiconductor memory device in the related art includes an address pad 1, a decoder 2 for decoding an address signal from the address pad 1, a memory cell array 3, a control pad 4 and a controller 5. The controller 5 detects an address transition signal ATD from the input address signals and outputs various control signals in accordance with a control signal from the control pad 4. A current mode latch sense amplifier 6 amplifys data from the memory cell array 3, and an output unit 7 externally outputs the amplified data. As shown in FIG. 4, the related art current mode latch sense amplifier 6 is configured with a differential amplifier structure in which a sense amplifier equalizing signal SAEQ is connected as a rated voltage source.
The data reading operation of the related art semiconductor memory device will now be described. When an address signal AD inputted through the address pad 1 is transited, the decoder 2 decodes the address signal AD and outputs a cell access signal CA as shown in FIG. 2D so that a corresponding word line WL is activated.
In addition, the controller 5 detects the address transition detection signal ATD from the address signal AD. The controller 5 generates various control signals based on the address transition signal ATD in accordance with the control signal from the control pad 4.
In particular, an equalizing signal EQ, a sense amplifier enable signal SAE, and a sense amplifier equalizing signal SAEQ are respectively generated for precharging the bit line BL and a common data line DL. The bit line BL and the common data line DL are equalized by a voltage (i.e., 1/2 Vcc) by the equalizing signal EQ as shown in FIG. 2C. Generally, data for cells are carried on the bit line for a predetermined time t1 as shown in FIG. 2D. Thereafter, the data decays.
As a result, an electric potential (i.e., data) of a cell connected with the word line WL is carried on a corresponding bit line /BL, and the voltage of the bit line /BL drops as much as .DELTA.V according to the cell data as shown in FIG. 2E. The case where data "0" is stored in the cell is illustrated in FIG. 2E. At this time, the voltage of the bit line BL maintains a precharged voltage Vcc/2.
In addition, the current mode latch sense amplifier 6 remains equalized until the sense amplifier enable signal SAE is activated by the sense amplifier equalizing signal SAEQ as shown in FIG. 2G. Thereafter, when a predetermined electric potential charge is formed between the bit line BL and the bit line /BL, the current mode latch sense amplifier 6 detects the output data DATA and DATAB from the memory cell array 3. The current mode latch sense amplifier 6 externally outputs the detected data through the output unit 7 in accordance with the sense amplifier enable signal SAE as shown in FIG. 2F.
The latch type sense amplifier has an advantage of low power consumption since the direct current flowing in the sense amplifier is removed after the data of the cell is read. However, when the cell access signal CA and the sense amplifier enable signal SAE as shown in FIG. 3 are mismatched by an inputted noise, the latch type sense amplifier outputs an invalid data depending on its characteristic. Such timing mismatches occur more frequently in high speed devices.
When PMOS transistors PM3 and PM4 and NMOS transistors NM4 and NM5 are turned on as shown in FIG. 4, the current mode latch sense amplifier 6 maintains an equalized state. At this time, since the data DATA and DATAB from the memory cell array 3 are carried on the bit line in accordance with the cell access signal CA shown in FIG. 3C, an electric potential difference .DELTA.V1 is formed between the bit line BL and the bit line /BL as shown in FIG. 3D.
The current mode latch sense amplifier 6 can output an invalid data when the activated sense amplifier enable signal SAE is input when electric potential difference .DELTA.V1 is smaller than a minimum predetermined electric potential difference Vsen for reading normal data. To overcome the invalid data problem, the width of the address transition signal ATD must be increased, which decreases an operational speed of the data reading circuit.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.